1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a method of manufacturing the non-volatile semiconductor device.
2. Related Background Art
FIGS. 1A and 1B show a conventional cell structure of a non-volatile semiconductor memory device such as UV PROM, OTP (One-Time PROM), EEPROM, Flash EEPROM.
As illustrated in FIG. 1A, the conventional non-volatile memory cell is constructed of a pair of element isolation regions 402 on a semiconductor substrate 401, cell forming regions separated by the element isolation regions 402, gate oxide layer 403 formed over this cell forming region, a floating gate 404 provided on the gate oxide layer 403, and a control gate electrode 406 provided through the floating gate 404 and an insulating layer 405. Further, an inter-poly insulating layer 407 and a BPSG layer 410 are provided on the control gate electrode 406. Moreover, a wiring layer 412 composed of Al etc is provided, and a passivation layer 413 is then provided thereon.
FIG. 1B is a sectional view taken along the line A-A' in FIG. 1A. The reference numerals 408 and 409 designate a source diffusion layer region and a drain diffusion layer region, respectively. The Al wiring layer 412 is connected via a contact hole to the source or drain region.
Let VCG be an electric potential of the control gate electrode 406 (which is hereinafter referred to as a control gate potential), VFG be an electric potential of the floating gate electrode 404 (which is hereinafter be termed a floating gate potential), and Vsub be an electric potential of the semiconductor substrate 401 (which is hereinafter be called a substrate potential), and further let C1 be a capacity between the semiconductor substrate 401 and the floating gate electrode 404 (which is hereinafter be referred to as an inter substrate-floating gate capacity), and C2 be a capacity between the floating gate electrode 404 and the control gate electrode 406 (which is hereinafter be termed an inter floating gate-control gate capacity), wherein an equivalent circuit of the prior art memory cell can be expressed as shown in FIG. 2. From this equivalent circuit, the floating gate potential can be given such as: ##EQU1##
At this time, the following is called a coupling ratio: ##EQU2##
Namely, the capacity components C1, C2 are assumed to be constants, in which case the floating gate potential VFG is determined by the control gate potential VCG and the coupling ratio. Writing and erasing to and from the memory cell are conducted depending on this floating gate potential VFG. The writing and erasing operations with respect to each of the memory cells will be explained.
The EPROM among the non-volatile semiconductor memory devices involves the use of an injection of channel hot electrons in the writing process and ultraviolet rays in the erasing process. Further, the OTP involves the use of the injection of channel hot electrons in the writing process as in the case of the EPROM, and no erasing process is done because of being sealed in a package. On the other hand, the EEPROM and the Flash EEPROM are each defined as an electrically erasable and programmable read only memory, and involve the use of the above-described channel hot electron injection or a Fowler-Noldheim current (hereinafter referred to as an FN tunnel current) in the writing process. Further, the erasing process is executed based on the FN tunnel current.
The channel hot electron injection is conducted using the channel hot electrons generated with pinchoff in the vicinity of the drain of the channel region by setting, e.g., the control gate potential to 10V, a drain voltage to 7V and a source voltage to an earth potential. At this time, as shown in the formula 1, the hot electrons are injected into the floating gate by the floating gate potential determined by the control gate potential VCG, the inter substrate-floating gate capacity C1 and the inter floating gate-control gate capacity C2.
The writing and erasing based on the FN tunnel current entail an injection and an emission of electric charges by applying an electric field as high as 6 MV/cm or larger to the floating gate electrode 404 and the inter semiconductor substrate gate insulating layer 403. As for the EEPROM, this gate insulating layer 403 is generally called a tunnel oxide layer 404 a thickness of which is on the order of 10 nm. For generating the FN tunnel current, a high voltage must be applied to this tunnel oxide layer 403. For example, if the coupling ratio shown in the formula 2 is approximately 0.6, a voltage as high as approximately 20 V must be applied to the control gate electrode or the semiconductor substrate 401.
Thus, the typical non-volatile memory requires the high voltage for the writing and erasing processes, and for this reason a peripheral circuit is hard to be downsized in terms of attaining its high integration. Further, if a power supply voltage is single, an internal step-up circuit must be incorporated thereinto, and this might lead to a first problem in which it is difficult to downsize the LSI.
Another problem is a deterioration of the tunnel oxide layer in the case of the writing and erasing processes based on the FN tunnel current. This deterioration is caused by the electrons being trapped into the oxide layer due to a passage of the FN current. This trapping might deteriorate writing/erasing characteristics of the memory cell or might cause a fluctuation of a threshold value Vth, resulting in a data mis-judgement or a writing/erasing enable state, which becomes a cause of a detect. Especially, this phenomenon, if there exists a thin region in the tunnel oxide layer, might get conspicuous because of the electric current being concentrated on this thin region. Normally, a thick field oxide layer is formed for the device separation, however, the tunnel oxide layer at the edge of the field oxide layer tends to be formed thinner by over several % than other regions (IEEE Trans, Electron Device (USA) Vol. 42, No.12).
FIG. 3 is an enlarged view showing a field oxide layer edge 414 in FIGS. 1A and 1B, wherein a thinned region 501 exists at the edge of LOCOS. Therefore, it follows that the deterioration advances in the thinned region 501.
Further, a tendency in recent years is that trench isolation is adopted for a device separation. FIG. 4 shows a structure of a memory cell in which the trench isolation is adopted for the EEPROM. The memory cell is constructed of a pair of device isolation regions 602 on a semiconductor substrate 601, a cell forming region separated by the device isolation region 602, a gate oxide layer 603 formed on this cell forming region, a floating gate 604 formed on the gate oxide layer 603, and a control gate electrode 606 provided via the floating gate 604 and the insulating layer 605. Further, an inter-poly insulating layer 607 and a BPSG layer 610 are provided on the control gate electrode 406. Moreover, a wiring layer 612 of Al etc is provided, and then a passivation layer 613 is provided. FIG. 5 is an enlarged view illustrating a trench corner 614 in FIG. 4. As shown in FIG. 5, an electric field concentrates at the trench corner, and a deterioration of withstanding pressure of the tunnel oxide layer might be thereby caused.
Thus, when executing the writing/erasing processes based on the FN tunnel current, a second problem might also arise, wherein the tunnel oxide layer is deteriorated due to the concentration of the electric field at the LOCOS edge or at the trench corner.